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Jadavpur University DSP Validation

Jadavpur University — DSP Validation Project Proposal

Section titled “Jadavpur University — DSP Validation Project Proposal”

Source: newdocs/Jadavpur_University_Proposal_Sections_3_to_7.docx Date: 2026-03-02

Design, configure, validate, and freeze a robust Digital Signal Processing (DSP) architecture for industrial vibration monitoring using IEPE accelerometers and/or advanced MEMS vibration modules with embedded ADC and DSP capabilities.

  • Establish a mathematically correct and industry-compliant signal chain from sensor to feature output
  • Define and freeze sampling rate, anti-alias filtering, FFT scaling, windowing, and feature extraction parameters
  • Validate RMS, Peak, Crest Factor, Envelope, Kurtosis and FFT outputs against known mechanical references
  • Develop a repeatable validation framework for lab-scale test rigs
  • Prepare validated data outputs suitable for integration with edge and cloud systems
  • IEPE signal conditioning validation
  • MEMS SPI interface validation (if applicable)
  • Verification of sampling rate and decimation configuration
  • Digital high-pass filtering (>= 1 Hz)
  • Band-limited RMS computation (e.g., 1-1000 Hz)
  • FFT implementation with correct amplitude scaling
  • Envelope processing using bandpass + rectification + low-pass method
  • Spike energy and kurtosis computation
  • Test rig validation under controlled mechanical excitation
  • Repeatability testing (+/- 5% RMS tolerance)
  • Frequency accuracy validation (+/- 1% at 1X RPM)
  • Mathematical definitions of all computed parameters
  • DSP configuration freeze document
  • Final validation report
PhaseDescription
Phase 1 — System ReviewReview sensor physics, ADC configuration, and signal chain
Phase 2 — Algorithm ValidationMathematical verification of RMS, FFT scaling, window correction, and envelope detection
Phase 3 — Experimental ValidationData acquisition from controlled test rig, cross-validation of computed parameters with reference mechanical values
Phase 4 — Optimization & FreezeFinalization of DSP configuration and performance documentation
Phase 5 — Reporting & HandoverSubmission of validated configuration parameters and recommendations
  • Validated and operational DSP architecture document
  • Mathematical formulation document
  • Sampling and filtering configuration report with details
  • FFT scaling validation note with sample outputs
  • Envelope processing definition and validation results with sample outputs
  • Experimental validation dataset and operational results
  • Final technical report suitable for accurate and operational industrial deployment

This project directly supports Phase 3 (DSP Dual-Path Integration) of RAPID AI v2.0:

  • The validated DSP outputs (RMS, Peak, Crest Factor, Envelope, Kurtosis, FFT) map directly to the DSPMetrics model in schemas_v2.py
  • The tolerance thresholds (+/- 5% RMS, +/- 1% frequency) inform the DSP_TOLERANCE config values in config_v2.py
  • The freeze document will define the exact contract for what edge DSP devices send to RAPID AI
  • Module A v2’s _cross_validate_dsp() function compares these DSP outputs against internally recomputed values
  • The validation framework ensures DSP metrics sent to RAPID AI are trustworthy (supporting the “physics authority” principle)
DSP DeliverableRAPID AI StatusIntegration Point
RMS (band-limited)Module A recomputesDSPMetrics.overall_rms, cross-validated
PeakModule A recomputesDSPMetrics.peak, cross-validated
Crest FactorModule A recomputesDSPMetrics.crest_factor, cross-validated
KurtosisModule A recomputesDSPMetrics.kurtosis, cross-validated
Envelope RMSNot currently computedDSPMetrics.envelope_rms (new capability)
Spike EnergyNot currently computedDSPMetrics.spike_energy (new capability)
HF KurtosisNot currently computedDSPMetrics.hf_kurtosis (new capability)
FFT SpectrumPartial (Module A)Future: spectral cross-validation
Sampling/Filter configNot trackedFuture: DSP metadata in MeasurementPoint